S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 30

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

AB[16:13]
AB17
AB18
AB19
AB20
Page 24
S1D13505
X23A-A-001-14
Pin Name
I
I
I
I
I
Type
115-118
114
113
112
111
Pin #
C
C
C
C
C
Table 5-1: Host Interface Pin Descriptions (Continued)
Cell
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
RESET#
State
• For Philips PR31500/31700 Bus, these pins are connected to V
• For Toshiba TX3912 Bus, these pins are connected to V
• For PowerPC Bus, these pins input the system address bits 15
• For all other busses, these pins input the system address bits 16
See “Host Bus Interface Pin Mapping” for summary. See the respective
AC Timing diagram for detailed functionality.
• For Philips PR31500/31700 Bus, this pin inputs the IO write
• For Toshiba TX3912 Bus, this pin inputs the IO write command
• For PowerPC Bus, this pin inputs the system address bit 14 (A14).
• For all other busses, this pin inputs the system address bit 17 (A17).
See “Host Bus Interface Pin Mapping” for summary. See the respective
AC Timing diagram for detailed functionality.
• For Philips PR31500/31700 Bus, this pin inputs the IO read
• For Toshiba TX3912 Bus, this pin inputs the IO read command
• For PowerPC Bus, this pin inputs the system address bit 13 (A13).
• For all other busses, this pin inputs the system address bit 18 (A18).
See “Host Bus Interface Pin Mapping” for summary. See the respective
AC Timing diagram for detailed functionality.
• For Philips PR31500/31700 Bus, this pin inputs the card control
• For Toshiba TX3912 Bus, this pin inputs the card control register
• For PowerPC Bus, this pin inputs the system address bit 12 (A12).
• For all other busses, this pin inputs the system address bit 19 (A19).
See “Host Bus Interface Pin Mapping” for summary. See the respective
AC Timing diagram for detailed functionality.
• For the MIPS/ISA Bus, this pin inputs system address bit 20. Note
• For Philips PR31500/31700 Bus, this pin inputs the address latch
• For Toshiba TX3912 Bus, this pin inputs the address latch enable
• For PowerPC Bus, this pin inputs the system address bit 11 (A11).
• For all other busses, this pin inputs the system address bit 20 (A20).
See “Host Bus Interface Pin Mapping” for summary. See the respective
AC Timing diagram for detailed functionality.
through 18 (A[15:18]).
through 13 (A[16:13]).
command (/CARDIOWR).
(CARDIOWR*).
command (/CARDIORD).
(CARDIORD*).
register access (/CARDREG).
(CARDREG*).
that for the ISA Bus, the unlatched LA20 must first be latched before
input to AB20.
enable (ALE).
(ALE).
Description
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 01/02/02
DD
.
DD
.