TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 95

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

9.2
9.2.1
9.2.2
Time Base Timer Control Register
buzzer drive. Divider output is from DVO pin.
Divider Output (DVO)
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
(0036H)
Note:Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0").
TBTCR
Data output
fc/2
fc/2
fc/2
fc/2
Configuration
Control
The Divider Output is controlled by the Time Base Timer Control Register.
Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to
disable(DVOEN="0"), do not change the setting of the divider output frequency.
13
12
10
11
or fs/2
or fs/2
or fs/2
or fs/2
DVOEN
5
4
3
2
Divider output control register
DVOEN
DVOCK
DVOCK
7
(a) configuration
Output latch
A
B
C
D
D
MPX
2
S
Y
TBTCR
6
Divider output
enable / disable
Divider Output (DVO)
frequency selection: [Hz]
Q
DVOCK
DVOEN
5
Figure 9-3 Divider Output
(DV7CK)
4
Page 81
(TBTEN)
DVO pin
0: Disable
1: Enable
3
00
01
10
11
Port output latch
TBTCR<DVOEN>
DVO pin output
DV7CK = 0
2
NORMAL1/2, IDLE1/2 Mode
fc/2
fc/2
fc/2
fc/2
13
12
11
10
(TBTCK)
1
(b) Timing chart
DV7CK = 1
0
fs/2
fs/2
fs/2
fs/2
5
4
3
2
(Initial value: 0000 0000)
TMP86FH92DMG
SLEEP1/2
SLOW1/2
Mode
fs/2
fs/2
fs/2
fs/2
5
4
3
2
R/W
R/W