TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 125

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

Example :Setting the timer mode with source clock fc/2
11.3.5
Table 11-6 Source Clock for 16-Bit Timer Mode
DV7CK = 0
NORMAL1/2, IDLE1/2 mode
(fc = 16.0 MHz)
fc/2
fc/2
fc/2
fc/2
to form a 16-bit timer.
timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter continues counting. Program the lower byte and upper byte in this order in
the timer register. (Programming only the upper or lower byte should not be attempted.)
11
7
5
3
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
Note 3: j = 3, 4
In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the
16-Bit Timer Mode (TC3 and 4)
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected
operation may not be obtained.
Source Clock
DV7CK = 1
fs/2
fc/2
fc/2
fc/2
LDW
DI
SET
EI
LD
LD
LD
3
7
5
3
(TTREG3), 927CH
(EIRH). 7
(TC3CR), 13H
(TC4CR), 04H
(TC4CR), 0CH
SLOW1/2,
SLEEP1/2
mode
fs/2
-
-
-
3
7
Page 111
fc = 16 MHz
[Hz], and generating an interrupt 300 ms later
128 μs
500 ns
8 μs
2 μs
; Sets the timer register (300 ms ÷ 2
; Enables INTTC4 interrupt.
; Sets the operating clock to fc/2
; (lower byte).
; Sets the 16-bit timer mode (upper byte).
; Starts the timer.
Resolution
fs = 32.768 kHz
244.14 μs
-
-
-
7
, and 16-bit timer mode
fc = 16 MHz
524.3 ms
131.1 ms
7
32.8 ms
/fc = 927CH).
8.39 s
Maximum Setting Time
TMP86FH92DMG
fs = 32.768 kHz
16 s
-
-
-