TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 121

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz)
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj
Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To
Note 3: j = 3, 4
is not in the shift register configuration in the programmable divider output mode, the new value programmed in
TTREGj is in effect immediately after programming. Therefore, if TTREGj is changed while the timer is running, an
expected operation may not be obtained.
change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the TCjCR<TFFj> setting
upon stopping of the timer.
Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3 ; Stops the timer.
CLR (TCjCR).7 ; Sets the PDOj pin to the high level.
LD
LD
LD
Setting port
(TTREG4), 3DH
(TC4CR), 00010001B
(TC4CR), 00011001B
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; 1/1024 ÷ 2
; Sets the operating clock to fc/2
; Starts TC4.
7
/fc ÷ 2 = 3DH
7
, and 8-bit PDO mode.
TMP86FH92DMG