TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 151

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TMP86xy92DMG

Manufacturer Part Number
TMP86xy92DMG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP86xy92DMG

Package
SSOP30
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
16
Ram Size
512
Driver Led
8
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
6
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
1
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
24
Power Supply (v)
4 to 5.5
13.9.4
13.9.5
UART2SR<RBFL> is cleared to “0” when the RD2BUF is read after reading the UART2SR.
shift register and data transmit starts, transmit data buffer empty flag UART2SR<TBEP> is set to “1”. The
UART2SR<TBEP> is cleared to “0” when the TD2BUF is written after reading the UART2SR.
RXD2 pin
RD2BUF
UART2SR<RBFL>
INTRXD2 interrupt
Shift register
Loading the received data in RD2BUF sets receive data buffer full flag UART2SR<RBFL> to "1". The
When no data is in the transmit buffer TD2BUF, that is, when data in TD2BUF are transferred to the transmit
Receive Data Buffer Full
Transmit Data Buffer Empty
UART2SR<RBFL>
RXD2 pin
RD2BUF
UART2SR<OERR>
INTRXD2 interrupt
Shift register
Note:Receive operations are disabled until the overrun error flag UART2SR<OERR> is cleared.
Note:If the overrun error flag UART2SR<OERR> is set during the period between reading the UART2SR and
reading the RD2BUF, it cannot be cleared by only reading the RD2BUF. Therefore, after reading the
RD2BUF, read the UART2SR again to check whether or not the overrun error flag which should have
been cleared still remains set.
Figure 13-8 Generation of Receive Data Buffer Full
Figure 13-7 Generation of Overrun Error
xxx0 **
yyyy
xxx0 **
yyyy
Final bit
Final bit
Page 137
xxxx0
xxxx0
*
*
Stop
Stop
1xxxx0
xxxx
1xxxx0
After reading UART2SR then
RD2BUF clears RBFL.
After reading UART2SR then
RD2BUF clears OERR.
TMP86FH92DMG

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