TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 66

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

5.1
P0 (P07 to P00) Port (High Current)
5.1
UART1 input/output, timer counter input/output and serial PROM mode control input. When using this port as serial
expansion interface output or UART1 output, set the output latch to 1. When using this port as a port output, the output
latch data (P0DR) is output to the P0 port.
respectively.
P0OUTCR register.
timer counter input, set the P0OUTCR register's corresponding bit to 0 after setting the P0DR to 1. The P0 port has
independent data input registers. To inspect the output latch status, read the P0DR register. To inspect the pin status,
read the P0PRD register.
PROM Mode Setting".
P0 (P07 to P00) Port (High Current)
The P0 port is an 8-bit input/output port shared with external interrupt input, serial expansion interface input/output,
When reset, the output latch (P0DR) and the push-pull control register (P0OUTCR) are initialized to 1 and 0,
The P0 port allows its output circuit to be selected between N-channel open-drain output or push-pull output by the
The P0 port has programmable internal Pull-up resistance to be controlled by P0PUCR registers.
When using this port as a port input, external interrupt input, serial expansion interface input, UART1 input and
In the serial PROM mode, P01 pin used as a BOOT/RXD1 pin, P00 pin used as a TXD1 pin. For details, see "Serial
Data input (P0PRD)
Data output (P0DR)
Data input (P0DR)
P0OUTCRi input
Control output
Control input
P0OUTCRi
P0PUCRi
OUTEN
STOP
Output latch
D
D
Q
Q
Figure 5-2 P0 Port
Page 52
VDD
P0i
Note: i = 7 to 0
TMP86FH92DMG