TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 170

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

15.5
I
2
C Bus Control
15.5.7
SDA pin
SCL pin
to “0” by a hardware if the bit is “0”. In the master mode, after an acknowledge signal is returned from the slave
device, the TRX is cleared to “0” by a hardware if a transmitted direction bit is “1”, and is set to "1" by a hardware
if it is “0”. When an acknowledge signal is not returned, the current condition is maintained.
"Table 15-2 TRX changing conditions in each mode" shows TRX changing conditions in each mode and TRX
value after changing
recognized. They are handled as data just after generating a start condition. The TRX is not changed by a hardware.
output on a bus after generating a start condition by writing “1” to the MST, TRX, BB and PIN. It is necessary
to set ACK to “1” beforehand.
PIN, and “0” to the BB. Do not modify the contents of MST, TRX, BB and PIN until a stop condition is generated
on a bus.
a stop condition is generated after releasing the SCL line.
when a start condition on a bus is detected (Bus Busy State) and is cleared to “0” when a stop condition is detected
(Bus Free State).
When a stop condition on the bus or an arbitration lost is detected, the TRX is cleared to “0” by the hardware.
When a serial bus interface circuit operates in the free data format, a slave address and a direction bit are not
When the BB (Bit5 in SBISRB) is “0”, a slave address and a direction bit which are set to the SBIDBR are
When the BB is “1”, sequence of generating a stop condition is started by writing “1” to the MST, TRX and
When a stop condition is generated and the SCL line on a bus is pulled-down to low level by another device,
The bus condition can be indicated by reading the contents of the BB (Bit5 in SBISRB). The BB is set to “1”
Figure 15-5 Start Condition Generation and Slave Address Generation
Start/stop condition generation
Table 15-2 TRX changing conditions in each mode
Start condition
Master
Mode
Slave
Mode
Mode
Figure 15-6 Stop Condition Generation
Direction Bit
SDA pin
SCL pin
A6
1
"0"
"1"
"0"
"1"
A5
2
A received slave address is the
A4
same value set to I2CAR
Slave address and the direction bit
3
ACK signal is returned
Page 156
Conditions
A3
4
Stop condition
A2
5
A1
6
TRX after Changing
A0
7
"0"
"1"
"1"
"0"
R/W
8
TMP86FH92DMG
Acknowledge signal
9