TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 174

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

15.6
Data Transfer of I
15.6.3
SCL pin
SDA pin
PIN
INTSBI
interrupt request
Write to SBIDBR
15.6.3.1
SCL pin
SDA pin
PIN
INTSBI
interrupt request
whether the mode is a master or slave.
2
C Bus
Check the MST by the INTSBI interrupt process after an 1-word data transfer is completed, and determine
1-word data transfer
Figure 15-9 Start Condition Generation and Slave Address Transfer
(1)
(2)
Check the TRX and determine whether the mode is a transmitter or receiver.
When the MST is “1” (Master mode)
generate a stop condition (Described later) and terminate data transfer.
bits, set the BC, set the ACK to “1”, and write the transmitted data to the SBIDBR. After writing the
data, the PIN becomes “1”, a serial clock pulse is generated for transferring a next 1 word of data from
the SCL pin, and then the 1 word of data is transmitted. After the data is transmitted, and an INTSBI
interrupt request occurs. The PIN become “0” and the SCL pin is set to low level. If the data to be
transferred is more than one word in length, repeat the procedure from the LRB test above.
the received data from the SBIDBR (Reading data is undefined immediately after a slave address is
sent). After the data is read, the PIN becomes “1”. A serial bus interface circuit outputs a serial clock
pulse to the SCL pin to transfer next 1-word of data and sets the SDA pin to “0” at the acknowledge
signal timing.
Test the LRB. When the LRB is “1”, a receiver does not request data. Implement the process to
When the LRB is “0”, the receiver requests next data. When the next transmitted data is other than 8
When the next transmitted data is other than of 8 bits, set the BC again. Set the ACK to “1” and read
When the TRX is “1” (Transmitter mode)
When the TRX is “0” (Receiver mode)
Figure 15-10 Example of when BC = “000”, ACK = “1”
Start condition
D7
A6
1
1
D6
2
A5
2
D5
3
A4
3
Slave address + Direction bit
Page 160
D4
4
A3
4
D3
5
A2
5
D2
6
A1
6
D1
7
A0
7
D0
R/W
8
8
TMP86FH92DMG
9
9
Acknowledge
signal from a
receiver
Acknowledge
signal from a
slave device