TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 214

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

19.6
Operation Mode
Note 8: If an error occurs during the reception of a password address or a password string, TMP86FH92DMG stops UART com-
Note 9: To rewrite data to Flash memory addresses at which data (including FFH) is already written, make sure to erase the
Description of RAM loader mode
munication and enters the halt condition. In this case, initialize TMP86FH92DMG by the RESET pin and reactivate the
serial PROM mode.
existing data by "sector erase" or "chip erase" before rewriting data.
1. The 1st through 4th bytes of the transmitted and received data contains the same data as in the flash
2. In the 5th byte of the received data contains the RAM loader command data (60H).
3. When the 5th byte of the received data contains the operation command data shown in Table 19-6, the
4. The 7th through m’th bytes of the transmitted and received data contain the same data as in the flash
5. The m’th + 1 through n’th - 2 bytes of the received data contain the binary data in the Intel Hex format.
6. The n’th - 1 and n’th bytes contain the checksum upper and lower bytes. For details on how to calculate
7. After transmitting the checksum to the external controller, the boot program jumps to the RAM address
memory writing mode.
device echoes back the value which is the same data in the 6th byte position (in this case, 60H). If the
5th byte does not contain the operation command data, the device enters the halt condition after sending
3 bytes of operation command error code (63H).
memory writing mode.
No received data is echoed back to the external controller. After receiving the start mark (3AH for “:”)
in the Intel Hex format, the device starts data record reception. Therefore, the received data except 3AH
is ignored until the start mark is received. After receiving the start mark, the device receives the data
record, that consists of data length, address, record type, write data and checksum. The writing data of
the data record is written into RAM specified by address. Since the device starts checksum calculation
after receiving an end record, the external controller should wait for the checksum after sending the
end record. If a receiving error or Intel Hex format error occurs, the device enters the halts condition
without returning an error code to the external controller.
the SUM, refer to "19.8 Checksum (SUM)". The checksum is calculated only when the end record is
detected and no receiving error or Intel Hex format error occurs. After sending the end record, the
external controller judges whether the transmission is completed correctly by receiving the checksum
sent by the device.
that is specified by the first received data record.
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