TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 85

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TMP86xy92DMG

Manufacturer Part Number
TMP86xy92DMG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP86xy92DMG

Package
SSOP30
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
16
Ram Size
512
Driver Led
8
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
6
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
1
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
24
Power Supply (v)
4 to 5.5
8. Watchdog Timer (WDT)
8.1
noises or the deadlock conditions, and return the CPU to a system recovery routine.
request”. Upon the reset release, this signal is initialized to “reset request”.
Watchdog Timer Configuration
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious
The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “interrupt
When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt.
Note:Care must be taken in system design since the watchdog timer functions are not be operated completely due to
Internal reset
fc/2
fc/2
fc/2
fc/2
effect of disturbing noise.
23
21
19
17
or fs/2
or fs/2
or fs/2
or fs/2
15
13
11
9
WDTT
2
0034
WDTEN
Watchdog timer control registers
Figure 8-1 Watchdog Timer Configuration
H
WDTCR1
Clock
Clear
S R
Q
Binary counters
Writing
disable code
1
Controller
0035
2
H
WDTCR2
Page 71
Overflow
Writing
clear code
WDT output
WDTOUT
Reset release
Interrupt request
R
S
Q
TMP86FH92DMG
Reset
request
INTWDT
interrupt
request

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