TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 88

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

8.2
Watchdog Timer Control
Example :Disabling the watchdog timer
Example :Setting watchdog timer interrupt
8.2.3
8.2.4
in other procedures causes a malfunction of the micro controller.
by the binary-counter overflow.
master flag (IMF).
is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is held
pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the RETN
instruction, too many levels of nesting may cause a malfunction of the microcontroller.
Watchdog Timer Disable
Watchdog Timer Interrupt (INTWDT)
To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register
When WDTCR1<WDTOUT> is cleared to “0”, a watchdog timer interrupt request (INTWDT) is generated
A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt
When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt
To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.
Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.
Table 8-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz)
1. Set the interrupt master flag (IMF) to “0”.
2. Set WDTCR2 to the clear code (4EH).
3. Set WDTCR1<WDTEN> to “0”.
4. Set WDTCR2 to the disable code (B1H).
WDTT
00
01
10
11
DI
LD
LDW
LD
LD
DV7CK = 0
524.288 m
131.072 m
32.768 m
(WDTCR2), 04EH
(WDTCR1), 0B101H
SP, 023FH
(WDTCR1), 00001000B
2.097
NORMAL1/2 mode
Watchdog Timer Detection Time[s]
Page 74
: IMF ← 0
: Clears the binary counter
: WDTEN ← 0, WDTCR2 ← Disable code
: Sets the stack pointer
: WDTOUT ← 0
DV7CK = 1
62.5 m
250 m
4
1
62.5 m
SLOW
250 m
mode
4
1
TMP86FH92DMG