TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 56

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

3.4
Software Interrupt (INTSW)
Example 1 :Returning from address trap interrupt (INTATRAP) service program
Example 2 :Restarting without returning interrupt
3.4
3.3.3
3.4.1
is highest prioritized interrupt).
Software Interrupt (INTSW)
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
Use the SWI instruction only for detection of the address error or for debugging.
PINTxx:
PINTxx:
restarting address, during interrupt service program.
(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)
can be accepted immediately after the interrupt return instruction is executed.
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated
Interrupt return
Address error detection
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
Interrupt return instructions [RETI]/[RETN] perform as follows.
As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and
INTATRAP occurs again. When interrupt acceptance processing has completed, stacked data for PCL
and PCH are located on address (SP + 1) and (SP + 2) respectively.
instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2).
task is performed but not the main task.
POP
LD
PUSH
(interrupt processing)
RETN
INC
INC
INC
(interrupt processing)
LD
JP
1. Program counter (PC) and program status word (PSW, includes IMF)
are restored from the stack.
2. Stack pointer (SP) is incremented by 3.
WA
WA, Return Address
WA
SP
SP
SP
EIRL, data
Restart Address
[RETI]/[RETN] Interrupt Return
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; Recover SP by 2
;
; Alter stacked data
; RETURN
; Recover SP by 3
;
;
; Set IMF to “1” or clear it to “0”
; Jump into restarting address
TMP86FH92DMG