TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 68

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

5.2
P1 (P14 to P10) Port
5.2
and serial bus interface input/output. When using this port as divider output, UART2 output and serial bus interface
output, set the output latch to 1. When using this port as a port output, the output latch data(P1DR) is output to the P1
port.
spectively.
register.
P1OUTCR register’s corresponding bit to 0 after setting the P1DR to 1.
the pin status, read the P1PRD register.
P1 (P14 to P10) Port
The P1 port is a 5-bit input/output port shared with external interrupt input, divider output, UART2 input/output
When reset, the output latch (P1DR) and the push-pull control register(P1OUTCR) are initialized to 1 and 0,re-
The P1 allows its output circuit to be selected between N-channel open-drain or push-pull output by the P1OUTCR
The P1 port has programmable internal pull-up resistance to be controlled by P1PUCR.
When using this port as a port input, external interrupt input, UART2 input and serial bus interface input, set the
The P1 port has independent data input registers.To inspect the output latch status, read the P1DR register.To inspect
Data input (P1PRD)
Data output (P1DR)
Data input (P1DR)
P1OUTCRi input
Control output
Control input
P1OUTCRi
P1PUCRi
OUTEN
STOP
Output latch
D
D
Q
Q
Figure 5-3 P1 Port
Page 54
VDD
Note: i =
P1i
TMP86FH92DMG
4
to 0