TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 169

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

15.5.4
15.5.5
15.5.6
15.5.3.2
ALS (Bit0 in I2CAR) to “0”, and set the SA (Bits7 to 1 in I2CAR) to the slave address.
ALS to “1”. With a free data format, the slave address and the direction bit are not recognized, and they are
processed as data from immediately after start condition.
be cleared to “0”.
receiver, the TRX should be cleared to “0”. When data with an addressing format is transferred in the slave mode,
the TRX is set to "1" by a hardware if the direction bit (R/W) sent from the master device is “1”, and is cleared
When the serial bus interface circuit is used with an addressing format to recognize the slave address, clear the
When the serial bus interface circuit is used with a free data format not to recognize the slave address, set the
To set a master device, the MST (Bit7 in SBICRB) should be set to “1”. To set a slave device, the MST should
When a stop condition on the bus or an arbitration lost is detected, the MST is cleared to “0” by the hardware.
To set the device as a transmitter, the TRX (Bit6 in SBICRB) should be set to "1". To set the device as a
to low will, in the first place, invalidate a clock pulse of another master device which generates a high-level
clock pulse.
even if there are two or more masters on the same bus.
level. After detecting this situation, Master 2 resets counting a clock pulse in the high level and sets the SCL
pin to the low level.
Since Master 2 holds the SCL line of the bus at the low level, Master 1 waits for counting a clock pulse in
the high level. After Master 2 sets a clock pulse to the high level at point “c” and detects the SCL line of the
bus at the high level, Master 1 starts counting a clock pulse in the high level. Then, the master, which has
finished the counting a clock pulse in the high level, pulls down the SCL pin to the low level.
master device with the longest low-level period from among those master devices connected to the bus.
Slave address and address recognition mode specification
Master/slave selection
Transmitter/receiver selection
In the I
The serial bus interface circuit has a clock synchronization function. This function ensures normal transfer
The example explains clock synchronization procedures when two masters simultaneously exist on a bus.
As Master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of the bus becomes the low
Master 1 finishes counting a clock pulse in the low level at point “b” and sets the SCL pin to the high level.
The clock pulse on the bus is determined by the master device with the shortest high-level period and the
SCL pin (Master 1)
SCL pin (Master 2)
SCL (Bus)
Clock synchronization
2
C bus, in order to drive a bus with a wired AND, a master device which pulls down a clock pulse
Figure 15-4 Clock Synchronization
a
Count restart
Page 155
b
Wait
c
Count start
Count reset
TMP86FH92DMG