TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 144

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

13.2
Control
13.2
UART2 Control Register1
UART2CR1
(0022H)
monitored using the UART status register (UART2SR).
UART2 is controlled by the UART2 Control Registers (UART2CR1, UART2CR2). The operating status can be
Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive
Note 2: The transmit clock and the parity are common to transmit and receive.
Note 3: UART2CR1<RXE> and UART2CR1<TXE> should be set to “0” before UART2CR1<BRG> is changed.
Control
TXE
7
complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit
is enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
EVEN
STBT
BRG
RXE
TXE
PE
RXE
6
Transfer operation
Receive operation
Transmit stop bit length
Even-numbered parity
Parity addition
Transmit clock select
STBT
5
EVEN
4
PE
3
2
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000:
001:
010:
011:
100:
101:
110:
111:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
BRG
1
Disable
Enable
Disable
Enable
1 bit
2 bits
Odd-numbered parity
Even-numbered parity
No parity
Parity
fc/13 [Hz]
fc/26
fc/52
fc/104
fc/208
fc/416
TC3 (Input INTTC3)
fc/96
0
(Initial value: 0000 0000)
TMP86FH92DMG
Write
only