TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 78

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

7.2
Control
7.2
Voltage detection control register1
(002BH)
VDCR1
Detection Control Register 2 (VDCR2).
TMP86C993XB. For details, refer to the register descriptions below.
and VD2S bits are provided in the VDCR2 to support the emulation of voltage detection operation. Setting
VDCR2<VDxS> to 0 while VDCR2<VDxEN> is set to 1 generates an interrupt or a reset depending on the
VDCR2<VDxMOD> setting (x = 1, 2). In debugging the voltage detection circuit with the TMP86C993XB (devel-
opment tool), this function can be used to emulate interrupt/reset generation by inserting a write instruction to the
VDCR2 in a software program.
Control
The voltage detection circuit is controlled by the Voltage Detection Control Register 1 (VDCR1) and Voltage
The functions of the VDCR1 and VDCR2 vary between the TMP86FH92DMG and the emulation chip
The TMP86C993XB does not allow an interrupt or a reset to be generated by voltage detection. Instead, the VD1S
Please ensure that the final verification of software operation is conducted with the TMP86FH92DMG.
Note 1: The VDCR1 is initialized by a power-on reset or an external reset input.
Note 2: If VDCR1<VD2F> or VDCR1<VD1F> is cleared by software simultaneously as it is set by detection of a low-voltage
Note 3: To enable voltage detection 2 operation by setting VDCR2<VD2EN> to 1, VDCR1<VD2LVL> must be set to 01.
VD2LVL
VD1LVL
VD2SF
VD1SF
VD2F
VD2F
VD1F
7
condition, the setting operation overrides the clearing operation so that the bit is set to 1.
Voltage detection 2 flag
(Latches the state when VDD < VD2LVL)
(Note 2)
Voltage detection 2 status flag
(Indicates the relation between VDD and
VD2LVL when read.)
Voltage detection 2 level select
(Note 3)
Voltage detection 1 flag
(Latches the state when VDD < VD1LVL.)
(Note 2)
Voltage detection 1 status flag
(Indicates the relation between VDD and
VD1LVL when read.)
Voltage detection 1 level select
VD2SF
6
5
VD2LVL
4
VD1F
3
Page 64
00:
01:
10:
11:
00:
01:
10:
11:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
VD1SF
2
VDD ≥ VD2LVL
VDD < VD2LVL
Clearing the flag
- (Note 4)
VDD ≥ VD2LVL
VDD < VD2LVL
Reserved
2.9 to 3.3V
Reserved
Reserved
VDD ≥ VD1LVL
VDD < VD1LVL
Clearing the flag
- (Note 4)
VDD ≥ VD1LVL
VDD < VD1LVL
4.0 to 4.7V
Reserved
Reserved
2.9 to 3.3V
TMP86FH92DMG
Read
Read
Write
Write
1
VD1LVL
0
(Initial value: 0010 0000)
This bit is only read as 1 immedi-
ately (for 3 machine cycles) after a
0 is written to VDCR2<VD2S>. At
other times, it is always read as 0.
This bit has no meaning as voltage
detection is performed based on
the VDCR2<VD2S> setting.
This bit is only read as 1 immedi-
ately (for 3 machine cycles) after a
0 is written to VDCR2<VD1S>. At
other times, it is always read as 0.
This bit has no meaning as voltage
detection is performed based on
the VDCR2<VD1S> setting.
0:
1:
0:
1:
0:
1:
0:
1:
-
Writing a 0 to VDCR2
<VD2S> sets this bit to 1.
Clear the flag
- (Note 4)
-
Writing a 0 to VDCR2
<VD1S> sets this bit to 1.
Clear the flag
- (Note 4)
TMP86C993XB
Read
Write
Read
Write
TMP86FH92DMG
Read
Read
R/W
Only
R/W
R/W
R/W
only