TMP86xy92DMG Toshiba, TMP86xy92DMG Datasheet - Page 167

• Manufacturer Part Number: TMP86xy92DMG
• Manufacturer: Toshiba

Specifications of TMP86xy92DMG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4 to 5.5

15.5.1
Serial Bus Interface Status Register B
SBISRB
(0018H)
15.5.1.1
Table 15-1 SCL and SDA Pins Status in Acknowledgement Mode
MST
TRX
AAS
AD0
LRB
PIN
BB
AL
Acknowledgement mode specification
serial bus interface circuit is a master mode, an additional clock pulse is generated for an acknowledge signal.
In a slave mode, a clock is counted for the acknowledge signal.
receiver during additional clock pulse cycle. In the master receiver mode, the SDA pin is set to low level
generation an acknowledge signal during additional clock pulse cycle.
when a “GENERAL CALL” is received, the SDA pin is set to low level generating an acknowledge signal.
After the matching of slave address or the detection of “GENERAL CALL”, in the transmitter, the SDA pin
is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle.
In a receiver, the SDA pin is set to low level generation an acknowledge signal during additional clock pulse
cycle after the matching of slave address or the detection of “GENERAL CALL”
Master
Mode
Slave
To set the device as an acknowledgment mode, the ACK (Bit4 in SBICRA) should be set to “1”. When a
In the master transmitter mode, the SDA pin is released in order to receive an acknowledge signal from the
In a slave mode, when a received slave address matches to a slave address which is set to the I2CAR or
The Table 15-1 shows the SCL and SDA pins status in acknowledgment mode.
Acknowledgment mode (ACK = “1”)
MST
7
Master/slave selection status
monitor
Transmitter/receiver selection
status monitor
Bus status monitor
Interrupt service requests status
monitor
Arbitration lost detection monitor
Slave address match detection
monitor
"GENERAL CALL" detection
monitor
Last received bit monitor
SDA
TRX
6
When slave address matches
or a general call is detected
After matching of slave address
or general call
SCL
SDA
SCL
Pin
BB
5
PIN
4
0: Slave
1: Master
0: Receiver
1: Transmitter
0: Bus free
1: Bus busy
0: Requesting interrupt service
1: Releasing interrupt service request
0: -
1: Arbitration lost detected
0: -
1: Detect slave address match or "GENERAL CALL"
0: -
1: Detect "GENERAL CALL"
0: Last receive bit is "0"
1: Last receive bit is "1"
Page 153
Released in order to receive an
acknowledge signal.
Released in order to receive an
acknowledge signal.
AL
3
A clock is counted for the acknowledge signal.
Transmitter
An additional clock pulse is generated.
AAS
2
-
AD0
1
Set to low level generating an
acknowledge signal
Set to low level generating an
acknowledge signal.
Set to low level generating an
acknowledge signal.
LRB
0
Receiver
(Initial value: 0001 0000)
TMP86FH92DMG
Read
only