LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 448
LAN9311-NZW
Manufacturer Part Number
LAN9311-NZW
Description
Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
Manufacturer
Standard Microsystem (Smsc)
Datasheet
1.LAN9311-NU.pdf
(460 pages)
Specifications of LAN9311-NZW
Package
128XVTQFP
Phy/transceiver Interface
MII
Number Of Primary Switch Ports
2
Maximum Data Rate
100 Mbps
Internal Memory Buffer Size
32 KB
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.295 A
Maximum Power Dissipation
1070 mW
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Standard
Quantity:
2
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Microchip Technology
Quantity:
10 000
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Revision 1.7 (06-29-10)
15.5.5
A[x:5], END_SEL
SYMBOL
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
ah
nCS, nRD
D[15:0]
A[4:1]
PIO Burst Read Cycle Timing
Please refer to
Note: A host PIO burst read cycle begins when both nCS and nRD are asserted. The cycle ends
Note: A[1] must toggle, fresh data is supplied each time A[1] toggles.
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD Valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
when either or both nCS and nRD are de-asserted. These signals may be asserted and de-
asserted in any order.
t
asu
Section 8.5.5, "PIO Burst Reads," on page 108
Table 15.9 PIO Burst Read Cycle Timing Values
t
don
Figure 15.5 PIO Burst Read Cycle Timing
DESCRIPTION
t
acyc
t
csdv
DATASHEET
t
adv
t
acyc
448
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
t
adv
for a functional description of this mode.
MIN
13
45
0
0
0
0
t
adv
t
acyc
t
TYP
ah
SMSC LAN9311/LAN9311i
t
doh
t
MAX
doff
t
csh
30
40
9
Datasheet
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS
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