LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 111

• Manufacturer Part Number: LAN9311-NZW
• Description: Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
8.5.8
D[15:0] (INPUT)
PIO Writes
PIO writes are used for all LAN9311/LAN9311i write cycles. PIO writes can be performed using Chip
Select (nCS) or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted.
The cycle ends when either or both nCS and nWR are de-asserted. Either or both of these control
signals must de-assert between cycles for the period specified in
Values,” on page
control signals must be de-asserted between cycles for the period specified. The PIO write cycle is
illustrated in the functional timing diagram in
The END_SEL signal has the same timing characteristics as the address lines.
Please refer to
for PIO write operations.
nCS, nWR
END_SEL
A[x:1]
Figure 8.7 Functional Timing for PIO Write Operation
Section 15.5.8, "PIO Write Cycle Timing," on page 451
451. They may be asserted and de-asserted in any order. Either or both of these
DATASHEET
111
Figure
VALID
VALID
8.7.
VALID
Table 15.12, “PIO Write Cycle Timing
for the AC timing specifications
Revision 1.7 (06-29-10)