LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 234
LAN9311-NZW
Manufacturer Part Number
LAN9311-NZW
Description
Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
Manufacturer
Standard Microsystem (Smsc)
Datasheet
1.LAN9311-NU.pdf
(460 pages)
Specifications of LAN9311-NZW
Package
128XVTQFP
Phy/transceiver Interface
MII
Number Of Primary Switch Ports
2
Maximum Data Rate
100 Mbps
Internal Memory Buffer Size
32 KB
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.295 A
Maximum Power Dissipation
1070 mW
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Standard
Quantity:
2
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 234 of 460
- Download datasheet (5Mb)
Revision 1.7 (06-29-10)
14.2.6.3
BITS
31:8
7
6
5
4
3
2
RESERVED
Port 0 Hard-wired Flow Control (HW_FC_MII)
When set to “1”, the Host MACs RX FIFO level is connected to the switch
engine’s transmitter and the switch engines RX FIFO level is connected to
the Host MACs transmitter. This achieves lower latency flow control.
Note:
Port 0 Backpressure Enable (BP_EN_MII)
This bit enables/disables the generation of half-duplex backpressure on
switch Port 0.
0: Disable backpressure
1: Enable backpressure
Port 0 Current Duplex (CUR_DUP_MII)
This bit indicates the actual duplex setting of the switch Port 0.
0: Full-Duplex
1: Half-Duplex
Port 0 Current Receive Flow Control Enable (CUR_RX_FC_MII)
This bit indicates the actual receive flow setting of switch Port 0
0: Flow control receive is currently disabled
1: Flow control receive is currently enabled
Port 0 Current Transmit Flow Control Enable (CUR_TX_FC_MII)
This bit indicates the actual transmit flow setting of switch Port 0.
0: Flow control transmit is currently disabled
1: Flow control transmit is currently enabled
Port 0 Receive Flow Control Enable (RX_FC_MII)
When the MANUAL_FC_MII bit is set, or Virtual Auto-Negotiation is
disabled, this bit enables/disables the detection of full-duplex Pause packets
on switch Port 0.
0: Disable flow control receive
1: Enable flow control receive
Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII)
This read/write register allows for the manual configuration of the switch Port 0(Host MAC) flow control.
This register also provides read back of the currently enabled flow control settings, whether set
manually or Auto-Negotiated. Refer to
additional information.
Note: The flow control values in the
All other flow control methods must be disabled when using this
feature. (MANUAL_FC_MII should be set, TX_FC_MII,
RX_FC_MII, and BP_EN_MII should be cleared. FCANY, FCADD,
FCBRD, and FCMULT in the AFC_CFG register should be
cleared).
Register (VPHY_AN_ADV)," on page 253
Offset:
1A8h
DESCRIPTION
DATASHEET
Section 14.2.8.5, "Virtual PHY Auto-Negotiation Advertisement
Section 6.2.3, "Flow Control Enable Logic," on page 58
234
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Size:
are not affected by the values of this register.
32 bits
TYPE
R/W
R/W
R/W
SMSC LAN9311/LAN9311i
RO
RO
RO
RO
Note 14.12
Note 14.13
Note 14.13
Note 14.13
Note 14.14
DEFAULT
Datasheet
0b
-
for
Related parts for LAN9311-NZW
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Ethernet Switch 3-Port 10Mbps/100Mbps 56-Pin QFN EP
Manufacturer:
Standard Microsystem (Smsc)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystem (Smsc)
Datasheet: