LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 225

• Manufacturer Part Number: LAN9311-NZW
• Description: Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
BITS
13
12
11
10
9
8
7
6
Alternate MAC Address 1 Enable Port 0(Host MAC)
(MAC_ALT1_EN_MII)
This bit enables/disables the alternate MAC address 1 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 0
Alternate MAC Address 2 Enable Port 0(Host MAC)
(MAC_ALT2_EN_MII)
This bit enables/disables the alternate MAC address 2 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 0
Alternate MAC Address 3 Enable Port 0(Host MAC)
(MAC_ALT3_EN_MII)
This bit enables/disables the alternate MAC address 3 on Port 0.
0: Disables alternate MAC address on Port 0
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 0
User Defined MAC Address Enable Port 0(Host MAC)
(MAC_USER_EN_MII)
This bit enables/disables the auxiliary MAC address on Port 0. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
0: Disables auxiliary MAC address on Port 0
1: Enables auxiliary MAC address as a PTP address on Port 0
Lock Enable RX Port 0(Host MAC) (LOCK_RX_MII)
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 0 is ready set due to a previous capture.
0: Disables RX Port 0 Lock
1: Enables RX Port 0 Lock
Note:
Lock Enable TX Port 0(Host MAC) (LOCK_TX_MII)
This bit enables/disables the TX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX
interrupt for Port 0 is ready set due to a previous capture.
0: Disables TX Port 0 Lock
1: Enables TX Port 0 Lock
Note:
RESERVED
Lock Enable GPIO 9 (LOCK_GPIO_9)
This bit enables/disables the GPIO 9 lock. This lock prevents a 1588 capture
from overwriting the Clock value if the 1588_GPIO9 interrupt in the
Interrupt Status and Enable Register (1588_INT_STS_EN)
due to a previous capture.
0: Disables GPIO 9 Lock
1: Enables GPIO 9 Lock
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
DESCRIPTION
DATASHEET
225
is already set
1588
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b
1b
1b
1b
-