LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 251
LAN9311-NZW
Manufacturer Part Number
LAN9311-NZW
Description
Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
Manufacturer
Standard Microsystem (Smsc)
Datasheet
1.LAN9311-NU.pdf
(460 pages)
Specifications of LAN9311-NZW
Package
128XVTQFP
Phy/transceiver Interface
MII
Number Of Primary Switch Ports
2
Maximum Data Rate
100 Mbps
Internal Memory Buffer Size
32 KB
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.295 A
Maximum Power Dissipation
1070 mW
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.8.3
31:16
BITS
15:0
RESERVED
(See
PHY ID
This field contains the MSB of the Virtual PHY OUI
Virtual PHY Identification MSB Register (VPHY_ID_MSB)
This read/write register contains the MSB of the Virtual PHY Organizationally Unique Identifier (OUI).
The LSB of the Virtual PHY OUI is contained in the
(VPHY_ID_LSB).
Note 14.23 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 14.24 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.
Note
14.23)
Offset:
Index (decimal):
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
1C8h
2
DESCRIPTION
DATASHEET
251
Size:
(Note
14.24).
Virtual PHY Identification LSB Register
32 bits
TYPE
R/W
RO
Revision 1.7 (06-29-10)
DEFAULT
0000h
-
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