LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 246

• Manufacturer Part Number: LAN9311-NZW
• Description: Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Revision 1.7 (06-29-10)
14.2.8
INDEX #
31
0
1
2
3
4
5
6
Virtual PHY
This section details the Virtual PHY System CSR’s. These registers provide status and control
information similar to that of a real PHY while maintaining IEEE 802.3 compatibility. The Virtual PHY
registers are addressable via the memory map, as described in
MII management protocol (IEEE 802.3 clause 22). When accessed serially, these registers are
accessed indirectly through the
Data Register (HMAC_MII_DATA)
clause 22. When being accessed serially, the Virtual PHY will respond when the PHY address equals
the address assigned by the phy_addr_sel_strap configuration strap, as defined in
Addressing," on page
Table
Virtual PHY functionality and operation information, see
Note: All Virtual PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management
Note: When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII
VPHY_AN_LP_BASE_ABILITY
14.4. For more information on the Virtual PHY access modes, refer to section
VPHY_BASIC_STATUS
VPHY_SPEC_CTRL_STATUS
register set. All functionality and bit definitions comply with these standards. The IEEE 802.3
specified register index (in decimal) is included under the LAN9311/LAN9311i memory mapped
offset of each Virtual PHY register as a reference. For additional information, refer to the IEEE
802.3 Specification.
management of PHY’s.
VPHY_BASIC_CTRL
VPHY_AN_ADV
VPHY_AN_EXP
VPHY_ID_MSB
Table 14.4 Virtual PHY MII Serially Adressable Register Index
VPHY_ID_LSB
SYMBOL
82. A list of all Virtual PHY register indexes for serial access can be seen in
Host MAC MII Access Register (HMAC_MII_ACC)
DATASHEET
via the MII serial management protocol specified in IEEE 802.3
Virtual PHY Basic Control Register,
Virtual PHY Basic Status Register,
Virtual PHY Identification MSB Register,
Virtual PHY Identification LSB Register,
Virtual PHY Auto-Negotiation Advertisement Register,
Section 14.2.8.5
Virtual PHY Auto-Negotiation Link Partner Base Page Ability
Register,
Virtual PHY Auto-Negotiation Expansion Register,
Section 14.2.8.7
Virtual PHY Special Control/Status Register,
246
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Section 14.2.8.6
Section 7.3, "Virtual PHY," on page
REGISTER NAME
Table
14.1, as well as serially via the
Section 14.2.8.2
Section 14.2.8.1
Section 14.2.8.4
Section 14.2.8.3
SMSC LAN9311/LAN9311i
Section 14.2.8.8
Section 7.1.1, "PHY
and
Section
Host MAC MII
Datasheet
96.
14.4. For