LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 36

• Manufacturer Part Number: LAN9311-NZW
• Description: Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Chapter 4 Clocking, Resets, and Power Management
Revision 1.7 (06-29-10)
4.1
4.2
The LAN9311/LAN9311i includes a clock module which provides generation of all system clocks as
required by the various sub-modules of the device. The LAN9311/LAN9311i requires a fixed-frequency
25MHz clock source for use by the internal clock oscillator and PLL. This is typically provided by
attaching a 25MHz crystal to the XI and XO pins as specified in
page
clock source. If a single-ended source is selected, the clock input must run continuously for normal
device operation. The internal PLL generates a fixed 200MHz base clock which is used to derive all
LAN9311/LAN9311i sub-system clocks.
In addition to the sub-system clocks, the clock module is also responsible for generating the clocks
used for the general purpose timer and free-running clock. Refer to
Timer & Free-Running Clock," on page 162
Note: Crystal specifications are provided in
The LAN9311/LAN9311i provides multiple hardware and software reset sources, which allow varying
levels of the LAN9311/LAN9311i to be reset. All resets can be categorized into three reset types as
described in the following sections:
The LAN9311/LAN9311i supports the use of configuration straps to allow automatic custom
configurations of various LAN9311/LAN9311i parameters. These configuration strap values are set
upon de-assertion of all chip-level resets and can be used to easily set the default parameters of the
chip at power-on or pin (nRST) reset. Refer to
detailed information on the usage of these straps.
Note: The LAN9311/LAN9311i EEPROM Loader is run upon a power-on reset, nRST pin reset, and
Table 4.1
following sections for detailed information on each of these reset types.
Clocks
Resets
—Power-On Reset (POR)
—nRST Pin Reset
—Digital Reset (DIGITAL_RST)
—Soft Reset (SRST)
—Port 2 PHY Reset
—Port 1 PHY Reset
—Virtual PHY Reset
Chip-Level Resets
Multi-Module Resets
Single-Module Resets
454. Optionally, this clock can be provided by driving the XI input pin with a single-ended 25MHz
on page
digital reset. Refer to
information.
summarizes the effect of the various reset sources on the LAN9311/LAN9311i. Refer to the
454.
Section 10.2.4, "EEPROM Loader," on page 150
DATASHEET
36
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
for additional details.
Table 15.15, “LAN9311/LAN9311iCrystal Specifications,”
Section 4.2.4, "Configuration Straps," on page 40
Section 15.6, "Clock Circuit," on
Chapter 12, "General Purpose
SMSC LAN9311/LAN9311i
for additional
Datasheet
for