LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 109

• Manufacturer Part Number: LAN9311-NZW
• Description: Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
8.5.6
D[15:0] (OUTPUT)
RX Data FIFO Direct PIO Reads
In this mode only A[2:1] are decoded, and any read of the LAN9311/LAN9311i will read the RX Data
FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally
accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful
when the host processor must increment its address when accessing the LAN9311/LAN9311i.
Timing is identical to a PIO read and the FIFO_SEL and END_SEL signals have the same timing
characteristics as the address lines. An RX Data FIFO direct PIO read cycle begins when both nCS
and nRD are asserted. Either or both of these control signals must de-assert between cycles for the
period specified in
The cycle ends when either or both nCS and nRD are de-asserted. These signals may be asserted
and de-asserted in any order. Read data is valid as indicated in the functional timing diagram in
Figure
Note: Address lines A[2:1] are still used, and address lines A[9:3] are ignored.
Please refer to
AC timing specifications for RX Data FIFO direct PIO read operations.
Figure 8.5 Functional Timing for RX Data FIFO Direct PIO Read Operation
8.5.
END_SEL
FIFO_SEL
nCS, nRD
A[2:1]
A[x:3]
Section 15.5.6, "RX Data FIFO Direct PIO Read Cycle Timing," on page 449
Table 15.10, “RX Data FIFO Direct PIO Read Cycle Timing Values,” on page
(READ DATA FROM RX DATA FIFO)
DATASHEET
109
VALID
VALID
VALID
Revision 1.7 (06-29-10)
for the
449.