LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 261

• Manufacturer Part Number: LAN9311-NZW
• Description: Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.9.2
BITS
31:0
Byte Test (BYTE_TEST)
This field reflects the current byte ordering
Byte Order Test Register (BYTE_TEST)
This read-only register can be used to determine the byte ordering of the current configuration. Byte
ordering is a function of the host data bus width and endianess. Refer to
on page 99
Note: This register can be read while the LAN9311/LAN9311i is in the reset or not ready states.
Note: Either half of this register can be read without the need to read the other half.
The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum
write-to-read or read-to-read timing. Refer to
Write-Read Cycles," on page 102
Cycles," on page 106
Offset:
and
Section 8.4, "Host Endianess," on page 100
for additional information.
064h
DESCRIPTION
DATASHEET
and
Section 8.5.3, "Special Restrictions on Back-to-Back Read
261
Section 8.5.2, "Special Restrictions on Back-to Back
Size:
for additional information on byte ordering.
32 bits
Section 8.3, "Host Data Bus,"
TYPE
RO
Revision 1.7 (06-29-10)
DEFAULT
87654321h