LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 307
LAN9311-NZW
Manufacturer Part Number
LAN9311-NZW
Description
Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
Manufacturer
Standard Microsystem (Smsc)
Datasheet
1.LAN9311-NU.pdf
(460 pages)
Specifications of LAN9311-NZW
Package
128XVTQFP
Phy/transceiver Interface
MII
Number Of Primary Switch Ports
2
Maximum Data Rate
100 Mbps
Internal Memory Buffer Size
32 KB
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.295 A
Maximum Power Dissipation
1070 mW
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Standard
Quantity:
2
Company:
Part Number:
LAN9311-NZW
Manufacturer:
Microchip Technology
Quantity:
10 000
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.4.2.12
BITS
15:8
7
6
5
4
3
2
1
0
RESERVED
INT7_MASK
This interrupt mask bit enables/masks the ENERGYON interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT6_MASK
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated)
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT3_MASK
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT2_MASK
This interrupt mask bit enables/masks the Parallel Detection fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT1_MASK
This interrupt mask bit enables/masks the Auto-Negotiation page received
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
RESERVED
Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
This read/write register is used to enable or mask the various Port x PHY interrupts and is used in
conjunction with the
Index (decimal): 30
Port x PHY Interrupt Source Flags Register
DESCRIPTION
DATASHEET
307
Size:
16 bits
(PHY_INTERRUPT_SOURCE_x).
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b
0b
0b
0b
-
-
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