LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 108

• Manufacturer Part Number: LAN9311-NZW
• Description: Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Revision 1.7 (06-29-10)
8.5.5
D[15:0] (OUTPUT)
END_SEL
nCS, nRD
A[x:5]
A[4:1]
PIO Burst Reads
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO
burst reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Burst Read
begins when both nCS and nRD are asserted. Either or both of these control signals must de-assert
between bursts for the period specified in
page
asserted and de-asserted in any order. Read data is valid as indicated in the functional timing diagram
in
Note: A[1] must toggle during burst reads. Fresh data is supplied each time A[1] is toggled.
The endian select signal (END_SEL) has the same timing characteristics as the upper address lines.
Please refer to
specifications for PIO burst read operations.
Note: PIO burst reads are only supported for the RX Data FIFO. Burst reads from other registers are
Figure
448. The burst cycle ends when either or both nCS and nRD are de-asserted. They may be
not supported.
8.4.
Figure 8.4 Functional Timing for PIO Burst Read Operation
Section 15.5.5, "PIO Burst Read Cycle Timing," on page 448
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108
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Table 15.9, “PIO Burst Read Cycle Timing Values,” on
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SMSC LAN9311/LAN9311i
for the AC timing
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Datasheet