LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 195
LAN9311-NZW
Manufacturer Part Number
LAN9311-NZW
Description
Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
Manufacturer
Standard Microsystem (Smsc)
Datasheet
1.LAN9311-NU.pdf
(460 pages)
Specifications of LAN9311-NZW
Package
128XVTQFP
Phy/transceiver Interface
MII
Number Of Primary Switch Ports
2
Maximum Data Rate
100 Mbps
Internal Memory Buffer Size
32 KB
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.295 A
Maximum Power Dissipation
1070 mW
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.3.2
31:28
27:16
15:12
BITS
11:0
RESERVED
GPIO Direction 11-0 (GPIODIR[11:0])
These bits set the input/output direction of the 12 GPIO pins.
0: GPIO pin is configured as an input
1: GPIO pin is configured as an output
RESERVED
GPIO Data 11-0 (GPIOD[11:0])
When a GPIO pin is enabled as an output, the value written to this field is
output on the corresponding GPIO pin. Upon a read, the value returned
depends on the current direction of the pin. If the pin is an input, the data
reflects the current state of the corresponding GPIO pin. If the pin is an
output, the data is the value that was last written into this register. For
GPIOs 11-10 and 7-0, the pin direction is determined by the GPDIR bits of
this register. For GPIOs 9 and 8, the pin direction is determined by the
GPDIR bits and the 1588_GPIO_OE bits in the
Configuration Register
General Purpose I/O Data & Direction Register (GPIO_DATA_DIR)
This read/write register configures the direction of the 12 GPIO pins and contains the GPIO input and
output data bits.
Offset:
(GPIO_CFG).
1E4h
DESCRIPTION
DATASHEET
195
General Purpose I/O
Size:
32 bits
TYPE
R/W
R/W
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
0h
0h
-
-
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