S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 572

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

128 KByte Flash Module (S12XFTMR128K1V1)
All assigned bits in the FERCNFG register are readable and writable.
19.3.2.7
The FSTAT register reports the operational status of the Flash module.
1
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
572
Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see
Offset Module Base + 0x0005
Offset Module Base + 0x0006
Reset
DFDIE
Reset
SFDIE
Field
1
0
W
W
R
R
CCIF
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
1 An interrupt will be requested whenever the SFDIF flag is set (see
Flash Status Register (FSTAT)
0
1
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 19-10. Flash Error Configuration Register (FERCNFG)
0
0
0
6
6
Figure 19-11. Flash Status Register (FSTAT)
Table 19-14. FERCNFG Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
ACCERR
0
0
0
5
5
FPVIOL
0
0
4
4
Description
MGBUSY
0
0
3
3
Section
Section
Section
RSVD
19.3.2.8)
0
0
2
2
19.3.2.8)
19.3.2.8)
Freescale Semiconductor
DFDIE
0
0
1
1
1
MGSTAT[1:0]
Section
SFDIE
0
0
0
0
1
19.6).