S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 310

IC MCU 16BIT 128KB FLSH 112LQFP

S9S12XS128J1MAL

Manufacturer Part Number
S9S12XS128J1MAL
Description
IC MCU 16BIT 128KB FLSH 112LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S9S12XS128J1MAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12XS
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
91
Number Of Timers
12
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
DEMO9S12XSFAME, EVB9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S12XS128J1MAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale’s Scalable Controller Area Network (S12MSCANV3)
1. WUPIE and WUPE (see
2. Bus-off state is only defined for transmitters by the CAN standard (see Bosch CAN 2.0A/B protocol specification). Because
11.3.2.7
The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.
310
RSTATE[1:0]
TSTATE[1:0]
WUPIE
mechanism from stop or wait is required.
the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK,
the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see
Flag Register
CSCIE
OVRIE
RXFIE
Field
5-4
3-2
7
6
1
0
(1)
Wake-Up Interrupt Enable
0 No interrupt request is generated from this event.
1 A wake-up event causes a Wake-Up interrupt request.
CAN Status Change Interrupt Enable
0 No interrupt request is generated from this event.
1 A CAN Status Change event causes an error interrupt request.
Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state
changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to
indicate the actual receiver state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by receiver state changes.
01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state
10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”
11 Generate CSCIF interrupt on all state changes.
Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter
state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags
continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by transmitter state changes.
01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter
10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other
11 Generate CSCIF interrupt on all state changes.
Overrun Interrupt Enable
0 No interrupt request is generated from this event.
1 An overrun event causes an error interrupt request.
Receiver Full Interrupt Enable
0 No interrupt request is generated from this event.
1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
MSCAN Transmitter Flag Register (CANTFLG)
(CANRFLG)”).
changes for generating CSCIF interrupt.
receiver state changes for generating CSCIF interrupt.
state changes for generating CSCIF interrupt.
transmitter state changes for generating CSCIF interrupt.
Section 11.3.2.1, “MSCAN Control Register 0
Table 11-12. CANRIER Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
Description
(CANCTL0)”) must both be enabled if the recovery
Section 11.3.2.5, “MSCAN Receiver
(2)
Freescale Semiconductor
state. Discard other

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