S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 106

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
Port Integration Module (S12XSPIMV1)
2.3.45
2.3.46
106
Address 0x025B
Address 0x025C
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
RDRP
PERP
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port P reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Port P pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
RDRP7
PPSP7
Port P Reduced Drive Register (RDRP)
Port P Pull Device Enable Register (PERP)
0
0
7
7
RDRP6
PPSP6
Figure 2-44. Port P Pull Device Enable Register (PERP)
0
0
6
6
Figure 2-43. Port P Reduced Drive Register (RDRP)
Table 2-42. RDRP Register Field Descriptions
Table 2-43. PERP Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
RDRP5
PPSP5
0
0
5
5
RDRP4
PPSP4
0
0
4
4
Description
Description
RDRP3
PPSP3
3
0
3
0
RDRP2
PPSP2
0
0
2
2
Freescale Semiconductor
RDRP1
PPSP1
Access: User read/write
Access: User read/write
0
0
1
1
RDRP0
PPSP0
0
0
0
0
1
1