S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 478

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Module Base + 0x0010 = TC0H
Module Base + 0x0011 = TC0L
Timer Module (TIM16B8CV2)
16.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0–7
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
478
Field
TOF
7
Reset
Reset
W
W
R
R
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit
requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one
(See also TCRE control bit explanation.)
0x0012 = TC1H
0x0014 = TC2H
0x0016 = TC3H
0x0013 = TC1L
0x0015 = TC2L
0x0017 = TC3L
(TCxH and TCxL)
Read/Write access in byte mode for high byte should takes place before low
byte otherwise it will give a different result.
Figure 16-22. Timer Input Capture/Output Compare Register x High (TCxH)
Figure 16-23. Timer Input Capture/Output Compare Register x Low (TCxL)
Bit 15
Bit 7
15
0
0
7
Bit 14
Bit 6
14
0
0
6
Table 16-17. TRLG2 Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
0x0018 = TC4H
0x001A = TC5H
0x001C = TC6H
0x001E = TC7H
0x0019 = TC4L
0x001B = TC5L
0x001D = TC6L
0x001F = TC7L
Bit 13
Bit 5
13
0
0
5
NOTE
Bit 12
Bit 4
12
0
0
4
Description
Bit 11
Bit 3
11
0
0
3
Bit 10
Bit 2
10
0
0
2
Freescale Semiconductor
Bit 9
Bit 1
0
0
9
1
Bit 8
Bit 0
0
0
0
0