S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 360

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Periodic Interrupt Timer (S12PIT24B4CV1)
12.4
Figure 12-19
control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger
interface.
12.4.1
As shown in
16-bit modulus down-counters and two 8-bit modulus down-counters. The 16-bit timers are clocked with
two selectable micro time bases which are generated with 8-bit modulus down-counters. Each 16-bit timer
is connected to micro time base 0 or 1 via the PMUX[3:0] bit setting in the PIT Multiplex (PITMUX)
register.
A timer channel is enabled if the module enable bit PITE in the PIT control and force load micro timer
(PITCFLMT) register is set and if the corresponding PCE bit in the PIT channel enable (PITCE) register
is set. Two 8-bit modulus down-counters are used to generate two micro time bases. As soon as a micro
time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter
will load its start value as specified in the PITMTLD0 or PITMTLD1 register and will start down-counting.
Whenever the micro timer down-counter has counted to zero the PITMTLD register is reloaded and the
connected 16-bit modulus down-counters count one cycle.
360
Bus
Clock
Functional Description
PFLMT
[0]
[1]
Timer
Figure 12-1
shows a detailed block diagram of the PIT module. The main parts of the PIT are status,
PITCFLMT Register
PITFLT Register
PITMUX Register
PITMLD0 Register
8-Bit Micro Timer 0
PITMLD1 Register
8-Bit Micro Timer 1
and
Figure 12-19. PIT24B4C Detailed Block Diagram
Figure
4
S12XS Family Reference Manual, Rev. 1.11
4
12-19, the 24-bit timers are built in a two-stage architecture with four
PMUX0
PFLT0
PFLT2
PFLT1
PFLT3
[1]
[2]
[3]
Timer 0
Timer 1
Timer 2
Timer 3
PITLD0 Register
PITCNT0 Register
PITLD1 Register
PITCNT1 Register
PITLD2 Register
PITCNT2 Register
PITLD3 Register
PITCNT3 Register
time-
out 3
time-
out 3
time-out 0
time-out 1
PIT24B4C
PITTF Register
PITINTE Register
Interrupt /
Trigger Interface
Freescale Semiconductor
Hardware
Trigger
Interrupt
Request
4
4