S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 290

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (ADC12B16CV1)
10.3.2.12 ATD Conversion Result Registers (ATDDRn)
The A/D conversion results are stored in 16 result registers. Results are always in unsigned data
representation. Left and right justification is selected using the DJM control bit in ATDCTL3.
If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must
be written with the compare values in left or right justified format depending on the actual value of the
DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be
stored there at the end of the conversion but is lost.
Read: Anytime
Write: Anytime
10.3.2.12.1 Left Justified Result Data (DJM=0)
10.3.2.12.2 Right Justified Result Data (DJM=1)
Table 10-15
result registers. Compare is always done using all 12 bits of both the conversion result and the compare
value in ATDDRn.
290
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11
0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11
0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15
Reset
Reset
W
W
R
R
Bit 11 Bit 10 Bit 9
15
15
0
0
0
shows how depending on the A/D resolution the conversion result is transferred to the ATD
For conversions not using automatic compare, results are stored in the result
registers after each conversion. In this case avoid writing to ATDDRn except
for initial values, because an A/D result might be overwritten.
14
14
0
0
0
Figure 10-15. Right justified ATD conversion result register (ATDDRn)
Figure 10-14. Left justified ATD conversion result register (ATDDRn)
13
13
0
0
0
Bit 8
12
12
0
0
0
Bit 11 Bit 10 Bit 9
Bit 7
S12XS Family Reference Manual, Rev. 1.11
11
11
0
0
Bit 6
10
10
0
0
Bit 5
0
0
9
9
NOTE
Bit 4
Bit 8
0
0
8
8
Bit 3
Bit 7
0
0
7
7
Bit 2
Bit 6
0
0
6
6
Bit 1
Bit 5
0
0
5
5
Bit 0
Bit 4
4
0
4
0
Bit 3
0
0
0
3
3
Freescale Semiconductor
Bit 2
0
0
0
2
2
Bi1 1
0
0
0
1
1
Bit 0
0
0
0
0
0