S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 473

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.2.8
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0008
Module Base + 0x0009
Reset
Reset
Field
OMx
OLx
7:0
7:0
W
W
R
R
OM7
OM3
Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For
Output Level — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
0
0
7
7
an output line to be driven by an OCx the OCPDx must be cleared.
an output line to be driven by an OCx the OCPDx must be cleared.
OMx
OL7
OL3
0
0
6
6
0
0
1
1
Figure 16-14. Timer Control Register 1 (TCTL1)
Figure 16-15. Timer Control Register 2 (TCTL2)
Table 16-8. TCTL1/TCTL2 Field Descriptions
Table 16-9. Compare Result Output Action
S12XS Family Reference Manual Rev. 1.11
OM6
OM2
OLx
0
1
0
1
0
0
5
5
OL6
OL2
0
0
4
4
action on the timer output signal
Clear OCx output line to zero
Description
Set OCx output line to one
Toggle OCx output line
No output compare
OM5
OM1
Action
0
0
3
3
OL5
OL1
0
0
2
2
Timer Module (TIM16B8CV2)
OM4
OM0
0
0
1
1
OL4
OL0
0
0
0
0
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