S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 210

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12X Debug (S12XDBGV3) Module
Table 6-28
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus these bits are ignored if tagged triggering is selected.
6.3.2.8.2
Read: Anytime. See
Write: If DBG not armed. See
210
Address: 0x0029
Bit[22:16]
Reset
Field
COMPE
6–0
Field
W
R
0
shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. .
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
0
0
7
Debug Comparator Address High Register (DBGXAH)
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
RWE Bit
Figure 6-15. Debug Comparator Address High Register (DBGXAH)
Table 6-26
0
0
1
1
1
1
= Unimplemented or Reserved
Bit 22
0
6
Table 6-27. DBGXCTL Field Descriptions (continued)
Table 6-28. Read or Write Comparison Logic Table
RW Bit
Table 6-26
for visible register encoding.
x
x
0
0
1
1
Table 6-29. DBGXAH Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
Bit 21
0
5
RW Signal
for visible register encoding.
0
1
0
1
0
1
Bit 20
0
4
Description
Description
Bit 19
RW not used in comparison
RW not used in comparison
0
3
Comment
No match
No match
Write
Read
Bit 18
0
2
Freescale Semiconductor
Bit 17
0
1
Bit 16
0
0