S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 504

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Voltage Regulator (S12VREGL3V3V1)
It is possible to generate with the API a waveform at an external pin by enabling the API by setting APIFE
and enabling the external access with setting APIEA. By setting APIES the waveform can be selected. If
APIES is set, then at the external pin a clock is visible with 2 times the selected API Period
If APIES is not set, then at the external pin will be a high pulse at the end of every selected period with the
size of half of the min period
17.4.9
This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and
signals are provided in
listed in
17.4.10 Description of Reset Operation
17.4.10.1 Power-On Reset (POR)
During chip power-up the digital core may not work if its supply voltage V
deassertion level (V
is kept high until V
The power-on reset is active in all operation modes of VREG_3V3.
17.4.10.2 Low-Voltage Reset (LVR)
For details on low-voltage reset, see
17.4.11 Interrupts
This section describes all interrupts originated by VREG_3V3.
The interrupt vectors requested by VREG_3V3 are listed in
priorities are defined at MCU level.
504
Table
Resets
17-13.
Autonomous periodical interrupt (API)
High Temperature Interrupt (HTI)
DD
PORD
Low-voltage interrupt (LVI)
exceeds V
Section 17.3, “Memory Map and Register
Interrupt Source
). Therefore, signal POR, which forces the other blocks of the device into reset,
Low-voltage reset
Power-on reset
Reset Source
(Table
PORD
S12XS Family Reference Manual, Rev. 1.11
17-10). See device level specification for connectivity.
Section 17.4.5, “Low-Voltage Reset
Table 17-14. Interrupt Vectors
. The MCU will run the start-up sequence after POR deassertion.
Table 17-13. Reset Sources
Available only in Full Performance Mode
LVIE = 1; available only in Full Performance
available only in Full Performance Mode
Local Enable
Always active
Table
Local Enable
APIE = 1
Definition”. Possible reset sources are
HTIE=1;
17-14. Vector addresses and interrupt
Mode
(LVR)”.
DD
is below the POR
Freescale Semiconductor
(Table
17-10).