S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 240

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12XE Clocks and Reset Generator (S12XECRGV1)
8.3.2.2
The REFDV register provides a finer granularity for the IPLL multiplier steps.
Read: Anytime
Write: Anytime except when PLLSEL = 1
The REFFRQ[1:0] bit are used to configure the internal PLL filter for optimal stability and lock time. For
correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in
(no locking and/or insufficient stability).
8.3.2.3
The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the
final divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 f
(divide by one).
240
Module Base + 0x0001
Reset
W
R
f REF
S12XECRG Reference Divider Register (REFDV)
S12XECRG Post Divider Register (POSTDIV)
0
7
=
REFFRQ[1:0]
Write to this register initializes the lock detector bit.
------------------------------------
(
REFDIV
f OSC
Figure
Figure 8-4. S12XECRG Reference Divider Register (REFDV)
0
6
+
1
)
Table 8-3. Reference Clock Frequency Selection
8-3. Setting the REFFRQ[1:0] bits wrong can result in a non functional IPLL
REFCLK Frequency Ranges
S12XS Family Reference Manual, Rev. 1.11
1MHz <= f
6MHz < f
2MHz < f
0
5
f
REF
REF
REF
>12MHz
REF
<= 12MHz
<= 6MHz
<= 2MHz
NOTE
0
4
0
3
REFFRQ[1:0]
REFDIV[5:0]
00
01
10
11
0
2
Freescale Semiconductor
0
1
PLL
= f
0
0
VCO