S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 253

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.1.1
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 64 (REFDIV+1) to output the REFCLK. The VCO output clock, (VCOCLK) is
fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2
x (SYNDIV +1)] to output the FBCLK. The VCOCLK is fed to the final programmable divider and is
divided in a range of 1,2,4,6,8,... to 62 (2*POSTDIV) to output the PLLCLK. See
The phase detector then compares the FBCLK, with the REFCLK. Correction pulses are generated based
on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the
internal filter capacitor, based on the width and direction of the correction pulse.
The user must select the range of the REFCLK frequency and the range of the VCOCLK frequency to
ensure that the correct IPLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK, and the REFCLK. Therefore, the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If IPLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check
the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during IPLL
start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, the PLLCLK can
be selected as the source for the system and core clocks. If the IPLL is selected as the source for the system
and core clocks and the LOCK bit is clear, the IPLL has suffered a severe noise hit and the software must
take appropriate action, depending on the application.
Freescale Semiconductor
4MHz
8MHz
4MHz
8MHz
4MHz
4MHz
4MHz
4MHz
f
OSC
•
•
•
The LOCK bit is a read-only indicator of the locked state of the IPLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆
when the VCO frequency is out of a certain tolerance, ∆
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
REFDIV[5:0]
$01
$03
$00
$00
$00
$01
$03
$03
IPLL Operation
2MHz
2MHz
4MHz
8MHz
4MHz
2MHz
1MHz
1MHz
f
REF
REFFRQ[1:0] SYNDIV[5:0]
Table 8-14. Examples of IPLL Divider Settings
01
01
01
10
01
01
00
00
S12XS Family Reference Manual Rev. 1.11
$18
$18
$09
$04
$03
$18
$18
$31
100MHz
100MHz
100MHz
100MHz
80MHz
80MHz
32MHz
50MHz
f
VCO
VCOFRQ[1:0] POSTDIV[4:0]
unl
S12XE Clocks and Reset Generator (S12XECRGV1)
.
11
11
01
01
00
11
01
11
$00
$00
$00
$00
$01
$01
$00
$01
Figure
Lock
8-15.
, and is cleared
100MHz 50 MHz
100MHz 50 MHz
80MHz
80MHz
16MHz
50MHz
50MHz
50MHz
f
PLL
40MHz
40MHz
25MHz
25MHz
25MHz
8MHz
f
BUS
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