S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 107

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
2.3.47
2.3.48
Freescale Semiconductor
Address 0x025D
Address 0x025E
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
Read: Anytime.
PPSP
Field
Field
PIEP
Reset
Reset
7-0
7-0
W
W
R
R
Port P pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device selected; rising edge selected
0 A pull-up device selected; falling edge selected
Port P interrupt enable—
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt enabled
0 Interrupt disabled (interrupt flag masked)
PPSP7
PIEP7
Port P Polarity Select Register (PPSP)
Port P Interrupt Enable Register (PIEP)
0
0
7
7
PPSP6
PIEP6
0
0
6
6
Figure 2-46. Port P Interrupt Enable Register (PIEP)
Figure 2-45. Port P Polarity Select Register (PPSP)
Table 2-44. PPSP Register Field Descriptions
Table 2-45. PIEP Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
PPSP5
PIEP5
0
0
5
5
PPSP4
PIEP4
0
0
4
4
Description
Description
PPSP3
PIEP3
3
0
3
0
PPSP2
PIEP2
0
0
Port Integration Module (S12XSPIMV1)
2
2
PPSP1
Access: User read/write
Access: User read/write
PIEP1
0
0
1
1
PPSP0
PIEP0
0
0
0
0
107
1
1