Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 95

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
10.3.2.7
10.3.2.8
DS0200-003
31:07
31:08
Offset 14h: SC_LSR – Line Status Register
Offset 18h: SC_GR – Global
Bits
Bits
06
05
04
03
02
01
00
07
06
05
04
03
02
01
00
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
Reset
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Description
Reserved
Transmitter Empty (TEMT): When set, THR and TSR are both empty.
Transmitter Holding Register Empty (THRE): When set, THR is empty.
Reserved
Framing Error (FE): When set, received character did not have a valid stop bit.
Parity Error (PE): When set, received data character does not have the correct even
or odd parity, as selected by the even parity select bit.
Overrun Error (OE): When set, CPU did not read data from RBR before the next
character was transferred into RBR, destroying the previous character.
Receive Data Ready (DR): When set, data is ready in the receive buffer.
Description
Reserved
WWT Direction (WWT_DIR): When set, this timer can be used for generating an
interrupt when the card is talking too early (based upon the value WWT_TO). When
cleared, WWT timeout is used when the CARD is talking too late (based upon
WWT_TO).
T1 Enable (T1_EN): When set, during reception no parity error is made on the I/O
line and no parity error is signaled, and during transmission parity bit is sent but no
error on the I/O line will be taken into account.
Reset Reception Counter (RST_REP_COUNT):
NUM_RX in reading mode.
Automatic Switch of RX to TX (RX_TO_TX): When set, and AUTO_SWT_EN is set
to ‘1’, auto switches from RX to TX in the case of CWT error or an ATR length error.
Automatic Switch TX to RX (TX_TO_RX): When set, auto switches from TX to RX
just after the parity and 2-ETU of stop bit. When cleared, switches after total guard
time.
Automatic Switch from TX to RX (AUTO_SWT_EN):
made when the number of data to send is reached and after the second stop bit of the
last send character. When cleared to ‘1’, see TX_TO_RX description.
Software Reset (SW_RST): When set, generates a software rest. Automatically
clears after the reset is complete.
Communication Direction (DR_EN): When set, receive. When cleared, transmit.
When set, automatically reset
When set, the switch is
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