Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 63

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
8.2
DS0200-003
DMA Source and Destination Addressing
For memory, DMA_SRCN/DMA_DESTN are addresses of the source and destination. For peripherals, all or
part of the address is fixed based upon DMA_CFGN.REQ.
destination addresses as well as the address increment controls are constructed based on
DMA_CFGN.REQ. A “P” in SINCR or DINCR indicates the field is programmable, while a ‘0’ indicates the
field is forced to zero.
The registers and fields involved with source data movement are:
0Bh – 10h
1Bh – 1Fh



REQ
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
DMA_SRCN → All bits
DMA_CNTN → All bits
DMA_CFGN → BURST, SWIDTH, SINCR
Rx Smart Card
Tx Smart Card
Mem-to-Mem
Rx UART 0
Rx UART 1
Rx UART 2
Rx Ext Req
Tx UART 0
Tx UART 1
Tx UART 2
Tx Ext Req
Transfer
Tx SHA-1
Rx SPI 0
Rx SPI 1
Tx SPI 0
Tx SPI 1
Rx MCR
Rx ADC
Tx LCD
Table 8-1: Source and Destination Address Construction
Source Address[31:0]
FFFF0h:DMA_SRC[11:0]
00b:DMA_SRC[29:0]
00b:DMA_SRC[29:0]
00b:DMA_SRC[29:0]
00b:DMA_SRC[29:0]
FFFE0000h
FFFE1000h
FFFE2000h
FFFEE000h
FFFF2008h
FFFF300Ch
FFFEF000h
Reserved
Reserved
Reserved
Reserved
The table below shows how the source and
P
0
0
0
0
0
P
0
0
0
P
P
Destination Address[31:0]
FFFF0h:DMA_DEST[11:0]
00b:DMA_DEST[29:0]
00b:DMA_DEST[29:0]
00b:DMA_DEST[29:0]
FFFED008h
FFFE0000h
FFFE1000h
FFFE2000h
FFFEE000h
FFFF9014h
FFFEF000h
Page 50
P
P
0
0
0
0
0
P
0
0
0