Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 103
Z32AN00NW200SG
Manufacturer Part Number
Z32AN00NW200SG
Description
IC ARM922T MCU 200MHZ 256-BGA
Manufacturer
Zilog
Series
Encore!® 32r
Datasheet
1.Z32AN00NW200SG.pdf
(196 pages)
Specifications of Z32AN00NW200SG
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
Peripherals
DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
For Use With
269-4713 - KIT DEV ENCORE 32 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
269-4717
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Z32AN Series Data Sheet
10.3.3.4
10.3.3.5
10.3.3.6
10.3.3.7
DS0200-003
31:08
06:04
31:16
15:00
31:18
17:00
31:18
17:00
Offset x4Ch: SC_TO_EN – Smart Card Timeout Enable
Offset x60h: SC_RST_LEN – Smart Card Reset Length
Offset x64h: SC_ATR_MIN_DLY – Smart Card ATR Minimum Delay
Offset x68h: SC_ATR_MAX_DLY – Smart Card ATR Maximum Delay
Bits
Bits
Bits
Bits
07
03
02
01
00
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
Reset
Reset
0000h
00000h
00000h
Reset
Reset
0
0
0
0
0
0
0
0
0
0
Description
Reserved
Master Interrupt Enable (MST): When set, use Interrupt Enable register
Reserved
Enable BGT Timeout Checking (BGT): When set, BGT timeout checking enabled
Enable BWT Timeout Checking (BWT): When set, BWT timeout checking enabled
Enable CWT Timeout Checking (CWT): When set, CWT timeout checking enabled
Enable WWT Timeout Checking (WWT): When set, WWT timeout checking enabled
Description
Reserved
Length (LENGTH): Defines the number of card clocks for reset from 0 to 65,535.
Description
Reserved
Value (VALUE): Defines number of card clocks for ATR minimum delay from 0 to
262,143 clocks.
Description
Reserved
Value (VALUE): Defines number of card clocks for ATR maximum delay from 0 to
262,143 clocks.
Page 90
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