Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 153

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
17.5.2.8
DS0200-003
31:08
Offset 014h: UARTx_LSR – UART Line Status Register
Bits
07
06
05
04
03
02
01
00
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
1
1
0
0
0
0
0
Description
Reserved
Error (ERR): When set, an error is detected in the FIFO. There is at least 1 parity,
framing or break indication error in the FIFO. Reset when register read and there are no
more bytes with error status in the FIFO.
Transmitter Empty (TEMT): When set, UARTx_THR/FIFO and transmit shift register
are empty; and the transmitter is idle. This bit cannot be set during the BREAK
condition. This bit only becomes 1 after the BREAK command is removed.
Transmit Holding Register Empty (THRE): When set to ‘1’, UARTx_THR/FIFO is
empty. This bit cannot be set to 1 during the BREAK condition. This bit only becomes 1
after the BREAK command is removed.
Break (BI): When set the receiver detects a BREAK condition on the receive line. This
bit is 1 if the duration of BREAK condition on the receive data is longer than one
character transmission time, the time depends on the programming of UARTx_LSR. In
case of FIFO only one null character is loaded into the receiver FIFO with the framing
error. The framing error is revealed whenever that particular data is read from the
receiver FIFO.
Framing Error (FE): When set, top character of the FIFO has a framing error. This bit
is set to 1 when the stop bit following the data/parity bit is logic 0.
Parity Error (PE): When set, character at the top of the receive FIFO has a parity
error.
Overrun Error (OE): When set, overrun error is detected. If FIFO is not enabled, the
data in UARTx_RBR was not read before the next character was transferred into
UARTx_RBR. If FIFO is enabled, the FIFO was full when an additional character was
received by the receiver shift register. The character in the receiver shift register is not
put into the receiver FIFO. Reset when register is read.
Data Ready (DR): If FIFO is not enabled, set to ‘1’ when a character is transferred
into UARTx_RBR from the receiver shift register. If FIFO is enabled, set to ‘1’ when a
character is received and transferred to the receiver FIFO.
Page 140