Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 62

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
Chapter 8: DMA Controller
8.1
DS0200-003
The DMA Controller is an AHB device that provides eight fully programmable, chaining capable DMA
channels that can transfer from peripheral-to-memory, memory-to-memory, or memory-to-peripheral. All
transactions consist of an AHB burst read into a DMA FIFO followed by an AHB burst write from the FIFO.
Each channel has the following features:
Channel Arbitration and Bursts
Once a channel has been programmed, it generates a request either immediately (memory-to-memory) or
when its associated peripheral requests DMA (memory-to-peripheral or peripheral-to-memory). The arbiter
grants on the basis of priority – a higher priority request is always granted. Within a priority level, requests
are granted on a round-robin basis. Once a channel’s request has been granted, it executes two steps:
Any required data alignment is achieved through the FIFO. Once granted, only an error condition interrupts
execution. The occurrence of a higher priority request will not. Once both steps are complete, re-arbitration
occurs. The fields EN, REQ, and PRI in DMA_CFGN are involved in arbitration.
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Full 32-bit source and destination addresses with 24-bit (16 MB) address increment capability
Up to 16 MB for each DMA buffer
Programmable burst size
Programmable priority
Interrupt upon count-to-zero
Abort on error
Burst movement of data from the source device into the FIFO.
Burst movement of data from the FIFO to the destination device.
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