Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 152

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
17.5.2.7
DS0200-003
31:08
Offset 010h – UARTx_MCR – UART Modem Control Registers
Bits
07
06
05
04
03
02
01
00
Type
RW
RW
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
Description
Reserved
UART Disable (UDISABLE): When set, UART FIFOs, state machines and status bits
are cleared. Setting this bit prior to updating control register settings ensures corrupted
characters will not be sent/received while updating control or baud rate settings.
Polarity (POLARITY): When set, invert polarity of TxD and RxD.
Multi-drop Mode (MDM): When set, multi-drop mode is enabled.
Loop Back Mode (LOOP): When set, Loop Back mode is enabled. Receive data is
disconnected connected to internal transmit data. The modem status input ports are
disconnected and the four bits of the modem control register are connected as modem
status inputs. The two modem control output ports (RTS and DTR) are set to their
inactive state.
Out 2 (OUT2): In loop back mode, this bit is connected to UARTx_MSR.DCD.
Out 1 (OUT1): In loop back mode, this bit is connected to UARTx_MSR.RI.
Request to Sent (RTS): In Normal operation, the RTS output port is the inverse of
this bit. In LOOP BACK mode, this bit is connected to the CTS bit in the UART Status
Register.
Data Terminal Ready (DTR): In Normal operation, the DTR output port is the
inverse of this bit. In LOOP BACK mode, this bit is connected to the DSR bit in the UART
Status Register.
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