Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 69

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
DS0200-003
17:16
15:14
13:11
08:04
03:02
Bits
10
09
01
00
Type
RW
RW
RW
RW
RW
RW
RW
RO
RO
Reset
00000
000
00
00
00
0
0
0
0
Description
Source Width (SWIDTH): Indicates the width of the source device. In most cases,
this will be the data width of each AHB transactions.
Pre-Scale Select (PS): Selects the Pre-Scale divider to use for the channel timer.
Time-Out Select (TO): Selects the number of pre-scale clocks seen by the channel
timer before a time-out conditions is generated for this channel. Since the pre-scalar
runs independent of the individual channel timers, the actual number of Pre-Scale clock
edges seen has a margin of error equal to a single Pre-Scale clock.
Request Wait Enable (WAIT): When cleared, the channel timer is enabled as soon
as the channel is enabled and PS is non-zero. Setting this bit delays the channel timer
enabled until at least one request has been received from the peripheral.
Reserved
Request Select (REQ):
channel.
Priority (PRI): Channel DMA priority. 00 = Highest Priority. 11 = Lowest priority
Reserved
Enable (EN): When set, the channel is enabled. After clearing to ‘0’, DMA_STAN.EN
determines when the channel is disabled. This bit is automatically cleared whenever
DMA_STAN.EN transitions from 1 to 0.
 00: byte
 01: half-word
 10: word
 11: reserved
 00: Disable timer for this channel.
 01: Pre-Scale is hclk divided by 256
 10: Pre-Scale is hclk divided by 64k
 11: Pre-Scale is hclk divided by 16M
 000: 3-4 Pre-Scale clocks
 001: 7-8 Pre-Scale clocks
 010: 15-16 Pre-Scale clocks
 011: 31-32 Pre-Scale clocks
 100: 63-64 Pre-Scale clocks
 101: 127-128 Pre-Scale clocks
 110: 255-256 Pre-Scale clocks
 111: 511-512 Pre-Scale clocks
0Bh – 0Fh
REQ
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
Rx External Peripheral
memory-to-memory
Rx Smart Card
Definition
Rx UART0
Rx UART1
Rx UART2
Reserved
Rx SPI 0
Rx SPI 1
Rx MCR
Rx ADC
N/A
Used to select which DMA request line is used for the
1Bh – 1Fh
REQ
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
Rx External Peripheral
Rx Smart Card
LCD Controller
Definition
Rx UART0
Rx UART1
Rx UART2
Tx SHA-1
Reserved
Reserved
Rx SPI 0
Tx SPI 1
N/A
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