Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 167

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
18.9.7 Offset 18h: SPI_DMA – SPI DMA Register
DS0200-003
17:16
01:00
30:27
26:24
23:21
19:18
14:11
10:08
07:05
03:02
Bits
31
20
15
04
RW
RW
Type
RW
WO
RW
WO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
11
11
000
000
0
0
0
0
0
0
0
0
0
0
Receive FIFO Level (RX_FIFO_LEVEL): Configures the number of filled RxFIFO
entries before activating an RxDMA request.
Transmit FIFO Level (TX_FIFO_LEVEL): Configures the number of free (empty)
TxFIFO entries before generating a DMA request.
Description
DMA Receive Enable (RXDMA): When cleared, disable RX DMA requests. When
set, enable RX DMA requests
Reserved
Receive FIFO Count (RX_FIFO_CNT): Indicates the number of entries in the RX
FIFO.
Reserved
Clear Receive FIFO (RX_FIFO_CLR):
Writes of ‘0’ have no effect. Always reads as ‘0’.
Reserved
DMA Transmit Enable (TXDMA): When cleared, disable TX DMA requests. When
set, enable TX DMA requests
Reserved
Transmit FIFO Count (TX_FIFO_CNT): Indicates the number of entries in the TX
FIFO.
Reserved
Transmit FIFO Clear (TX_FIFO_CLR): When written to ‘1’, resets the Tx FIFO.
Writes of ‘0’ have no effect. Always reads as ‘0’.
Reserved
 00: Request RxDMA when RxFIFO contains 1 entry
 01: Request RxDMA when RxFIFO contains 2 entries
 10: Request RxDMA when RxFIFO contains 3 entries
 11: Request RxDMA when RxFIFO contains 4 entries
 00: Request TxDMA when TxFIFO has 1 free entry
 01: Request TxDMA when TxFIFO has 2 free entries
 10: Request TxDMA when TxFIFO has 3 free entries
 11: Request TxDMA when TxFIFO has 4 free entries
 000: RxFIFO empty (0 entries)
 001: RxFIFO contains 1 entry
 010: RxFIFO contains 2 entries
 011: RxFIFO contains 3 entries
 100: RxFIFO contains 4 entries
 000: TxFIFO empty (0 entries)
 001: TxFIFO contains 1 entry
 010: TxFIFO contains 2 entries
 011: TxFIFO contains 3 entries
 100: TxFIFO contains 4 entries
When written to ‘1’, resets the Rx FIFO.
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