Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 57
Z32AN00NW200SG
Manufacturer Part Number
Z32AN00NW200SG
Description
IC ARM922T MCU 200MHZ 256-BGA
Manufacturer
Zilog
Series
Encore!® 32r
Datasheet
1.Z32AN00NW200SG.pdf
(196 pages)
Specifications of Z32AN00NW200SG
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
Peripherals
DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
For Use With
269-4713 - KIT DEV ENCORE 32 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
269-4717
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Part Number
Manufacturer
Quantity
Price
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Z32AN Series Data Sheet
7.4.1.4
7.4.1.5
DS0200-003
31:05
03:02
01:00
31:28
27:16
15:05
03:02
01:00
Offset 00Ch: SDR_APD – SDRAM Automatic Power-Down
Offset 010h: MEMC_GCFG – Memory Controller Global Configuration
Bits
Bits
04
04
Type
Type
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
Reset
Reset
FFFh
00
00
00
0
0
0
0
0
0
Description
Reserved
SDCLK Disable (CLK_DIS): Specifies whether SDCLK must be disabled (gated) as
part of the automatic power down sequence.
Mode (MODE): Selects type of power down mode of the SDRAM Controller.
Timer (TIMER): Specifies the number of SDCLKs after an access of SDRAM before
initiating the action specified in MODE.
Description
Reserved
Ready Time-out (READY_TIMEOUT):
results in an AHB bus error. 0-4k hclk cycles. 0-4k hclk cycles.
Reserved
Bus Zero Mode (BUS_ZERO): When set, MD[15:0] and SD[15:0] are driven “0”
when SDRAM and Memory Controller state machines are idle.
MD[15:0] and SD[15:0] are floating when SDRAM and Memory Controller State
Machines are idle.
FLCLK Divider (FLCLK_DIV): Specifies the divider to derive flclk from hclk:
Reserved
0: Do not disable SDCLK automatically
1: Disable SDCLK upon automatic power down time-out.
00: Disable Automatic Power Down
01: Automatic Pre-charge Power Down
10: Automatic Active Power Down
11: Automatic Self Refresh
00: 64 SDCLK cycles
01: 128 SDCLK cycles
10: 256 SDCLK cycles
11: 512 SDCLK cycles
00: divide hclk by 2
01: divide hclk by 4
10: divide hclk by 6
11: divide hclk by 8
Global READY time-out limit. Time-out
When cleared,
Page 44
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